CAVIAR
From July 2003 until Mai 2007 two positions in the Microelectronics Group were sponsored by the EU 5th Framework IST project CAVIAR. We are part of the the Department of Informatics at the University of Oslo. The CAVIAR project involved partners in Sevilla and Zürich. IMSE in Sevilla was the coordinator. They maintain the project homepage. The project did implement an AER communication framework and the individual partners made use of that framework (and still do) by developing AER sensory and processing chips that they were finally combined in a demonstrator system. This system did roboustly and rapidly track a rolling and jumping ball. the principal contributions of the group in Oslo fall into two categories:
- Competitive Hebbian learning for unsupervised classification of spatio-temporal spike patterns on an aVLSI chip with AER interface
- Consortium Standards Definitions ensuring Compatibility of the Devices Developped by the Partners
Competitive Hebbian learning for unsupervised classification of spatio-temporal spike patterns on an aVLSI chip with AER interface
We developped an AER-chip that is to be fed sequences of ball positions. It learns to classify those sequences that form ball trajectories, thus, providing higher level information (like 'fast ball from left to right', 'slow ball from left to right', 'hopping ball', 'ball about to bounce from a wall') to a further processing stage.
A central problem of implementing any kind of learning on an aVLSI chip is that of storing the learning state. The first publication that we wrote is, thus, concerned with a special memory cell that we developped for this purpose.
Publications that resulted from this project
- Adaptive WTA with an analog VLSI neuromorphic learning chip
P. Häfliger, in the IEEE Transactions on Neural Networks, accepted for publication in fall 2006
- High-Speed Serial AER on FPGA (With H. K. O. Berge, accepted for publication at ISCAS 2007, New orleans, USA)
- Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation, P. Häfliger and H. K. O. Berge, in the IEEE Transactions on Circuits and Systems II, 2007, vol. 54 (2), p 127-130
- AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems (With R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, Advances in Neural Information Processing Systems (NIPS), 2005) abstract, pdf.
- An Asynchronous 4-to-4 AER Mapper H. Kolle Riis and P. Häfliger, Conference paper at IWANN 2005 in Barcelona) abstract, pdf.
- A Foveated AER Imager Chip (With M. Azadmehr and J. P. Abrahamsen, Conference paper at ISCAS 2005 in Kobe) abstract, pdf.
- A Time Domain Winner-Take-All network of Integrate-and-Fire Neurons (With J. P. Abrahamsen and T. S. Lande, Conference paper ISCAS 2004 in Vancouver) abstract, pdf
- Spike Based Learning with Weak Multi-Level Static Memory (With H. Kolle Riis, Conference paper ISCAS 2004 in Vancouver) abstract, pdf
- A Multi-Level Static Memory Cell (With H. Kolle Riis, Conference paper ISCAS 2003 in Bangkok) abstract, pdf
Consortium Standards Definitions ensuring Compapility of the Devices Developped by the Partners
The central product of this contribution is a document that defines the CAVIAR consortium AER HW interface standards. We also want to make those standards freely available to other groups that are interested in exchanging AER hardware.
We also produced a generic AER PCB. Follow the link for a photograph. It connects AER chips that follow our pin out standards to an AER bus that also complies with our standards.
contact: 
last update: 5.7.2005
