Spike based learning

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Here we explore the possibilities, offered by the use of spiking neurons, in formulating learning rules. We especially consider causal relationships between pre- and postsynaptic spikes, as recently described in biological neurons as well by Henry Markram, J. Lübcke, M. Frotscher and B. Sakmann (in Science, vol. 275). Significant work on such learning rules has also been done by Wulfram Gerstner etal. and Wolfgang Maas etal.

We also put some emphasis on analog VLSI implementations of artificial synapses that use our learning rules. There we investigate the use of floating gates (FG) for the weight storage, because this technique offers permanent, power supply independent, long term storage of analog voltages. These properties will be very useful, when we move to real world applications. Unfortunately, the device matching properties of FG-storage cells in the standard, non-specialized CMOS processes that we have available, is bad and costly to improve in layout area. Learning algorithms, by there adaptibility, are rather robust against small mismatches. Nevertheless, we are currently also investigating other methods of analog storage.

Status

We formulated the Modified Riccati Rule (MRR). In addition to the sensitivity to causal relationships between pre- and postsynaptic spike, this rule implicitly (no extra step) normalizes the neurons weight vector.

Several hardware implementations have been tested. Some first versions with capacitive, volatile weight storage and later versions that use floating gates. The later FG synapse we also added to a biologically more accurate aVLSI model of a neuron: a 'silicon neuron' (publication:Floating gate analog memory for parameter and variable storage in a learning silicon neuron (Conference paper ISCAS'99) abstract, pdf, ps).

Most neuronal models with FG synaptic storage were placed on a multi neuron chip with address event in- and output (see SCX-project by A. Whatley) and FG parameter storage.

Detailed documentation of this project up to that point (2000) can now be found in my thesis.

After I concluded my thesis, my attention was somewhat diverted to other topics. That changed as we entered the CAVIAR project in June 2002, sponsored by the EU 5th Framework IST programme. We are now also exploiting alternative methods of analog storage (publication: A Multi-Level Static Memory Cell (With H. Kolle Riis, Conference paper ISCAS 2003 in Bangkok) abstract, pdf)


last update: 31.3.2003